The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also been accompanied by increased complexity in design and manufacturing of devices incorporating these ICs, and, for these advances to be realized, similar developments in device fabrication are needed.
Line edge roughness (LER) and/or line width roughness (LWR) are commonly formed when patterning line (or trench, contact hole, etc.) features during IC fabrication. They are particularly challenging when critical dimension (CD) of IC devices continue to decrease. LER and/or LWR may arise during exposure and development of resist material (or masking element) and may be transferred though multiple material layers during the patterning process, adversely affecting the final patterning results. Incorporating metal-containing layer(s) has improved etching selectivity during such patterning process; however, improvements in minimizing LER and/or LWR in these layers are still desirable.